This invention relates generally to high speed ECL gate circuits and more particularly, its relates to an improved dynamic ECL line driver circuit for driving line Loads having a significant capacitance.
As is generally known, emitter-coupled logic (ECL) logic circuits have inherently low gate propagation delay times. However, when an ECL gate circuit is used to drive line loads having large capacitance, there will be a significant increase in the propagation delay times as the load capacitance of the output line increases. As a result, this increased propagation delay will have an impact on degrading the high performance in such ECL gate circuits. A standard ECL line driver circuit of the prior art is shown in FIG. 1 and has been designated "prior art". The line driver circuit of FIG. 1 will be discussed more fully hereinafter.
One attempt to overcome the capacitive loading problem for ECL gate circuits has been to utilize an opposite (out-of-phase) phase signal to the input signal to enhance the current in the load current source. This approach requires a separate bias voltage generator for the load current source which has additional wiring, thereby increasing manufacturing cost. Further, such prior art attempt has the disadvantage in that it is susceptible to noise spikes on the voltage supply line which were undistinguishable from a transition signal at the collector of the out-of-phase transistor. Due to these noises spikes, the signal on the output terminal behaved in an unpredictable manner. A prior art ECL circuit employing this technique is shown in FIG. 2 of U.S. Pat. No. 4,539,493 issued on Sept. 3, 1985. The patentee of this patent is the same inventor as in the present application, and the patent is assigned to the same assignee as this application.
It would therefore be desirable to provide a dynamic ECL line driver circuit for driving line loads having significant capacitance which is insensitive to noise spikes on the supply voltage line and which does not require a separate bias voltage generator. The dynamic ECL line driver circuit of the present invention was found to possess a substantial reduction in the downgoing transition delay time.